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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GCSCR_EL3, Guarded Control Stack Control (EL3)</h1><p>The GCSCR_EL3 characteristics are:</p><h2>Purpose</h2>
        <p>Controls the Guarded control stack at EL3.</p>
      <h2>Configuration</h2><p>This register is present only when FEAT_GCS is implemented. Otherwise, direct accesses to GCSCR_EL3 are <span class="arm-defined-word">UNDEFINED</span>.</p><h2>Attributes</h2>
        <p>GCSCR_EL3 is a 64-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-63_10">RES0</a></td></tr><tr class="firstrow"><td class="lr" colspan="22"><a href="#fieldset_0-63_10">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-9_9">STREn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-8_8">PUSHMEn</a></td><td class="lr" colspan="1"><a href="#fieldset_0-7_7">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-6_6">EXLOCKEN</a></td><td class="lr" colspan="1"><a href="#fieldset_0-5_5">RVCHKEN</a></td><td class="lr" colspan="4"><a href="#fieldset_0-4_1">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-0_0">PCRSEL</a></td></tr></tbody></table><h4 id="fieldset_0-63_10">Bits [63:10]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-9_9">STREn, bit [9]</h4><div class="field"><p>Execution of the following instructions are trapped:</p>
<ul>
<li>GCSSTR.
</li><li>GCSSTTR.
</li></ul><table class="valuetable"><tr><th>STREn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of any of the specified instructions at EL3 cause a GCS exception.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-8_8">PUSHMEn, bit [8]</h4><div class="field">
      <p>Trap GCSPUSHM instruction.</p>
    <table class="valuetable"><tr><th>PUSHMEn</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Execution of a GCSPUSHM instruction at EL3 causes a Trap exception.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>This control does not cause any instructions to be trapped.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-7_7">Bit [7]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-6_6">EXLOCKEN, bit [6]</h4><div class="field"><p>Exception state lock.</p>
<p>Prevents <span class="instruction">MSR</span> instructions from writing to <a href="AArch64-elr_el3.html">ELR_EL3</a> or <a href="AArch64-spsr_el3.html">SPSR_EL3</a>.</p><table class="valuetable"><tr><th>EXLOCKEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>EL3 exception state locking disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>EL3 exception state locking enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><h4 id="fieldset_0-5_5">RVCHKEN, bit [5]</h4><div class="field">
      <p>Return value check enable.</p>
    <table class="valuetable"><tr><th>RVCHKEN</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Return value checking disabled at EL3.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Return value checking enabled at EL3.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-4_1">Bits [4:1]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-0_0">PCRSEL, bit [0]</h4><div class="field">
      <p>Guarded control stack procedure call return enable selection.</p>
    <table class="valuetable"><tr><th>PCRSEL</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Guarded control stack at EL3 is not PCR Selected.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Guarded control stack at EL3 is PCR Selected.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to <span class="binarynumber">0</span>.
</li></ul></div><div class="access_mechanisms"><h2>Accessing GCSCR_EL3</h2><p>Accesses to this register use the following encodings in the System register encoding space:</p><h4 class="assembler">MRS &lt;Xt&gt;, GCSCR_EL3</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b110</td><td>0b0010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    X[t, 64] = GCSCR_EL3;
                </p><h4 class="assembler">MSR GCSCR_EL3, &lt;Xt&gt;</h4><table class="access_instructions"><tr><th>op0</th><th>op1</th><th>CRn</th><th>CRm</th><th>op2</th></tr><tr><td>0b11</td><td>0b110</td><td>0b0010</td><td>0b0101</td><td>0b000</td></tr></table><p class="pseudocode">
if PSTATE.EL == EL0 then
    UNDEFINED;
elsif PSTATE.EL == EL1 then
    UNDEFINED;
elsif PSTATE.EL == EL2 then
    UNDEFINED;
elsif PSTATE.EL == EL3 then
    GCSCR_EL3 = X[t, 64];
                </p></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:07; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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